Is it possible to control whether the IOWarrior24 sends a ACK or a NACK during the I2C operations?
I was unable to find anything in the documentation that let me control this functionality described in the I2C Specification 2.1 Paragraph 7.2
The ACK or NACK occurs during the 9th clock cycle and is sometimes necessary to tell the slave device to not send anymore data. (A 24C02 EEProm has this functionality
Thanks for any advice you have....
IOW24-DG DLL
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Re: IOW24-DG DLL
No, not sending ACK does not really make a difference if the next thing is a stop condition.
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Re: IOW24-DG DLL
Thanks for the quick reply
I was hoping for another 'Bit' in the Report header that could control the ACK/NACK sequence, similar to the 'START' and 'STOP' bits.
Serial EEProms (24Cxx type) use the ACK/NACK to control whether you are reading 1 byte (NACK) or multiple bytes (ACK) with the final byte being a NACK to signify you don't want more data.
Having to send the STOP when you didn't have to just makes the I2C communication take that much longer for each byte you access.
Thanks for your assistance
I was hoping for another 'Bit' in the Report header that could control the ACK/NACK sequence, similar to the 'START' and 'STOP' bits.
Serial EEProms (24Cxx type) use the ACK/NACK to control whether you are reading 1 byte (NACK) or multiple bytes (ACK) with the final byte being a NACK to signify you don't want more data.
Having to send the STOP when you didn't have to just makes the I2C communication take that much longer for each byte you access.
Thanks for your assistance
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Re: IOW24-DG DLL
Not sending a stop would end the bus in a undefined state. Sending stop takes the same time as a single bit. Since IO-Warrior completely handles the read operation after receiving a single command there is no additional traffic on the USB to send the stop condition. On read operations you actually don't even have the choice to select if start and stop are generated since there is no IIC read operation for which omitting start or stop would make sense.